Exemplary embodiments of the present invention relate to a semiconductor device fabrication method, and more particularly, to a semiconductor device having metal gates and a method for fabricating the semiconductor device.
Semiconductor devices, operating at a high data rate, include both NMOSFETs and PMOSTFETs. Since the NMOSFET and the PMOSTFET both operate at a high speed, it is desired that a gate electrode of the NMOSFETs and a gate electrode of the PMOSFETs have a proper work function individually to have optimal characteristics. In other words, the work function of the gate electrode of the NMOSTFETs may approach the energy level of the edges of silicon conduction band, and the work function of the gate electrode of the PMOSTFETs may approach the energy level of the edges of silicon valence band. In this case, the channels of the NMOSFETs and the PMOSFETs may be formed as surface channels. Therefore, the NMOSFETs and the PMOSFETs may all operate at a high speed.
FIG. 1 illustrates a structure of a conventional semiconductor device.
Referring to FIG. 1, an isolation layer 12 is formed over a semiconductor substrate 11. The isolation layer 12 defines a first region 101 where an NMOSFET is formed and a second region 102 where a PMOSFET is formed in the semiconductor substrate 11. Over the first region 101, a first gate 103 is formed, and a second gate 104 is formed over the second region 102. The first gate 103 is formed by stacking a silicon oxide (SiO2) layer 13A, an N+-doped polysilicon layer 14A, and a tungsten (W) layer 15A. The second gate 104 is formed by stacking a silicon (SiO2) oxide layer 13B, a P+-doped polysilicon layer 14B, and a tungsten (W) layer 15B.
In accordance with the conventional semiconductor device, which is described above, the silicon oxide (SiO2) layers 13A and 13B are grown to have a thickness less than 30 Å for the purpose of increasing a drive current. However, a leakage current value may increase due to a direct tunneling effect. Accordingly, off-state characteristics may be deteriorated and thus there are limitations in applying the technology to low-power mobile products.
Moreover, the conventional technology may require complicated fabrication processes, such as a process of performing a polysilicon deposition, a lithography process, and an ion implantation process to be performed in order to form the N+-doped polysilicon layer 14A and the P+-doped polysilicon layer 14B, which are used as gate electrodes.
Also, a dopant of the P+-doped polysilicon layer 14B, such as boron, may penetrate into a gate insulation layer under the P+-doped polysilicon layer 14B, which is the silicon oxide (SiO2) layer 13B, and increase leakage current.
Furthermore, according to the conventional technology, since the gate electrodes are formed of the polysilicon layers doped with N-type and P-type impurities, their resistivity is high, and the operation speed of an NMOSFET and a PMOSFET may be lowered due to a depletion region formed in such gate electrodes.